Circuit chips receive a signal voltage at a signal input. In order to decide whether the received signal voltage is on a logical 1 or on a logical 0, the circuit chips compare the signal voltage to a reference voltage. If the signal voltage is above the reference voltage, a logical 1 will be detected and on the other side if the signal voltage is below the reference voltage, a logical 0 will be detected. Typically a plurality of circuit chips are connected to the same reference voltage. A memory module comprising a plurality of memory chips is an example for such a design.
FIG. 6 shows a computer memory system design according to the prior art. The memory system design comprises a memory module 600 and a memory controller 601. The memory module 600 comprises a plurality of memory chips 602a–602i. To be more specific, the memory module 600 comprises nine memory chips or DRAM chips 602a–602i. For reasons of clarity only the first two memory chips DRAM1 602a and DRAM2 602b, the middle memory chip DRAM5 602e and the last two memory chips DRAM8 602h and DRAM9 602i are provided with corresponding reference signs.
Each memory chip 602a to 602i comprises a signal input 604a to 604i which connects each memory chip 602a to 602i to a signal line 608. Further, each memory chip 602a to 602i comprises a reference signal input which connects each memory chip 602a to 602i to a reference voltage line 609 which is connected to the reference voltage supply Vref (Vref=receiver reference voltage). The signal line 608 is terminated by a termination resistance 616 to a termination voltage level Vtt. The termination resistance 616 is equal to a characteristic impedance of the signal line 608. The termination voltage Vtt is one half of a supply voltage level Vdd (not shown). (Vdd for modern memory modules typically is in range 1.5 to 3.3 V.) The memory modules 600a to 600i are connected to the signal line 608 by vias 622a to 622i and stubs 624a to 624i.  
Thus, FIG. 6 shows a fly-by net structure which is very spread in the computer memory system design, especially because it is a simple solution for a signal bus routing on a printed circuit board like the memory module 600. In a memory system design, it allows to deliver an address or data information to a plurality of memory chips 602a to 602i. 
The controller 601 generates a signal voltage which is applied on the signal line 608. The controller 601 comprises a signal driver 634, a driver resistance 636 (here the resistor is used just like a simplified model of the transistor driver) and, typically, a controller package 638. The controller 601 and the memory module 600 are arranged on a circuit board. A connection between the signal line 608 on the memory module 600 and the circuit board is provided by a connector 640.
The signal voltage applied to the signal line 608 by the controller 601 symmetrically changes around the termination voltage level Vtt which is equal to half the supply voltage level of the memory chips.
In a typical design, the driver resistance 636 is 15 ohm, the termination resistance 616 is 30 ohm. The characteristic impedance of the signal line 608 from the controller 601 to the first via 622a is 40 ohm and the characteristic impedance of the signal line 608 from the first via 622a to the termination resistance 616 is 60 ohm (but together with input capacitance of memory chips it gives about 30 Ohm of effective impedance). The length of the signal line 608 from the controller 601 to the connector 640 is typically 178 mm and the length from the connector 640 to the first via 622a is 25.4 mm. Additionally, there is a 7.5 mm long signal line 608 part between the connector 640 and the first via 622a comprising a characteristic impedance of 60 ohm. Portions of the signal line 608 between neighboring vias, like the portion between the first via 622a and the second via 622b is 15 mm. The length of the stubs 624a to 624i is 2.54 mm. The memory module 600, in this particular example, is a dual inline memory module (DIMM; DIMM=dual inline memory module) and comprises a plurality of signal layers. A motherboard lead-in and a DIMM lead-in at the connector 640 as well as via like the vias 622a to 622i are formed on an external signal layer. All other lines are formed on an internal layer.
FIG. 7 shows a DC resistor network model of the computer memory system described in FIG. 6. The lines, as shown in FIG. 6, are replaced by models for corresponding resistors. In particular, FIG. 7 illustrates a total resistance between each signal input 604a to 604i of each memory chip to the signal driver 634 and a resistance between neighboring signal inputs 604a to 604i. For reasons of clarity, only the first two signal inputs 604a, 604b, the fifth signal input 604h and the last signal input 604i are shown. Further, FIG. 7 shows the termination resistance 616 and the termination voltage Vtt and the driver resistance 636 as already described in FIG. 6. A resistance of a controller package, a motherboard lead-in and a connector (not shown in FIG. 7) are idealized by a package resistor 737. A lead-in resistor 738 and a lead-out resistor 739 modelize a resistance of the memory module lead-in and a memory module lead-out. Resistances 712a to 712h modelize the resistance of portions of the signal line shown in FIG. 6 between neighboring vias, the resistance of a via and a resistance of a stub to a memory chip as shown in FIG. 6.
Typically, the driver resistance 636 is 15 ohm, the package resistance plus lead-in trace resistance 737 is 0.8 ohm, the on DIMM lead-in resistance 738 is 0.08 ohm, the resistances (DRAM to DRAM trace) 712a to 712h are 0.1707 ohm each, the lead-out resistance 739 is 0.085 ohm and the termination resistance 616 is 30 ohm. A total resistance between the first signal input 604a, and the last signal input 604i is 1.36 ohm which is 8×0.1707 ohm. Resistance data are given for case of 0.1 mm wide and 0.045 mm thick copper trace.
According to the prior art, the signal driver 634 provides a signal voltage switching between 0 V and 1.5 V. The termination voltage Vtt is 0.75 V. Thus, there is always a DC current flowing through the resistors shown in FIG. 7. Between the first signal input 604a and the last signal input 604i there is a voltage drop due to the current through the resistors 712a to 712h. 
FIG. 8 shows the DC model as is shown and already described in FIG. 7 along with eye diagrams 850a, 850e, 850i. The first eye diagram 850a shows the signal voltage at the first signal input 604a, the second eye diagram 850e shows the signal voltage at the fifth signal input 604e and the third eye diagram 850i shows the signal voltage at the ninth signal input 604i. The signal input 604e represents the signal input of the middle memory chip as shown in FIG. 6. The signal input 604a represents the signal input of the first memory chip and the signal input 604i the signal input of the last memory chip as shown in FIG. 6. For reasons of clarity the eye diagrams 850a, 850e, 850i only show transitions of the signal voltage from the low voltage level to the high voltage level or from the high voltage level to the low voltage level.
The signal driver of the controller 601 provides a voltage signal which switches between 0 V and 1.5 V. The termination voltage Vtt is at 0.75 V. The eye diagrams 850a, 850e, 850i are centered around the termination voltage Vtt. The vertical extension of the data eyes (in this case it is an amplitude of the signal) decreases from the first data eye 850a taken from the first signal input 604a over the second data eye 850e, taken from the middle signal input 604e to the third data eye 850i taken from the last data signal 604i. The reason for this effect is the voltage drop at the resistances 712a to 712h between the signal inputs 604a to 604i as described in FIG. 7. The voltage drop is due to a DC current between the termination voltage Vtt and the controller 601.
FIG. 9 shows a diagram showing signal voltages at the signal inputs of all memory chips shown in FIG. 6. There are data eyes at all DRAM inputs simulated with equivalent resistive network are put in top of each other. As in FIG. 8, transitions from a high voltage level to a low voltage level and the low voltage level to the high voltage level are shown. As can be seen, all eyes are centered at 0.75 V which is the termination voltage Vtt. A first vertical extension 961, corresponding to the first data eye, is larger than the last vertical extension 962, corresponding to the last data eye.
Any variations of the driver resistance or the termination resistance (shown in FIG. 6) does not influence the symmetrical behavior of the signal voltages. Nevertheless, the termination voltage Vtt has the disadvantage of requiring an additional voltage source beside the supply voltage source in order to provide a stable termination voltage level. Alternatively, the termination voltage Vtt is generated from the supply voltage by a pair of additional resistors (not shown) which have the disadvantage of consuming a lot of power. Moreover a very low inductive printed circuit board trace or plane is necessary to distribute the termination voltage Vtt to all termination resistors (actually in this example peak current in one line is +/−30 mA. Number of the command-address traces is normally 27, then peak value of current consumed from the termination source could be +/−0.45 A). To provide a stable termination voltage level Vtt, a well capacitive coupling to ground is necessary. The same disadvantages apply to the reference voltage Vref.